1. Field of the Invention
The present invention generally relates to a shift register and a programmable logic circuit, and more particularly, to a chain-connected shift register and a programmable logic circuit using the chainconnected shift register which may be constructed with an extremely small size.
The present invention is further directed to a programmable logic circuit and a programmable-logic-circuit system constructed with a plurality of programmable logic circuits, whose logic functions are changeable during a circuit operation. Therefore, a number of realizable logic circuits in the programmable logic circuit may be significantly increased.
2. Description of the Related Art
For a programmable logic circuit, for example, a field programmable gate array (FPGA) is commonly well known. FIG. 1 shows a block diagram of a typical configuration example of the field programmable gate array (FPGA). The FPGA has a plurality of logic cells, each of which may program a desired logic circuit, and a plurality of wires which can flexibly connect the plurality of logic cells to each other. By providing configuration data describing a configuration of the logic circuit into each logic cell, a large number of logic circuits may be flexibly provided. For methods of storing the configuration data, at present, the following three types of FPGA are used.
I. SRAM-program-type FPGA: The configuration data is stored in a SRAM memory cell. Functions of the logic circuit may be repeatedly changed. When manufacturing the FPGA, there is no need for a specific process technique. PA1 II. Nonvolatile-memory-program-type FPGA: The configuration data is stored in a nonvolatile memory such as an EEPROM or a flash memory. In the same way as the SRAM-program-type FPGA, functions of the logic circuit may be repeatedly changed. However, when manufacturing the FPGA, there is a need for a specific process technique. PA1 III. Antifuse-program-type FPGA: According to the configuration data, conditions of switches (anti fuses) provided on an LSI chip are permanently determined. After programing is finished, functions of the logic circuit may not be changed. When manufacturing the FPGA, there is a need for a specific process technique. PA1 I. Individual flip-flop type: In the logic cell, the flip-flop is individually provided in addition to a programmable function unit. Input and output of the flip-flop are controlled by the configuration data. PA1 II. Program feedback type: In the programmable function unit provided in the logic cell, a feedback path is provided. When a connecting instruction is produced from the configuration data, the flip-flop is established.
Further, by flexibly connecting and combining a plurality of programmable logic circuits, a still further large number of logic circuits may be constructed, which are referred to as a programmable-logic-circuit system.
In addition, recently, in order to carry out a logic operation test of the large number of logic circuits on a circuit board which is in practical use, a hardware emulator is developed. In the hardware emulator, a plurality of FPGAs are connected to each other in a programed condition, and the large number of logic circuits are constructed. As compared to a software simulator operable in a work station, the hardware emulator is operable at a high speed more than 100 times the operation speed of the software simulator. Therefore, the hardware emulator may be widely used for developing a microprocessor, etc.
In the SRAM-program-type FPGA, the configuration data is commonly serially loaded into a configuration memory. Therefore, in general, the configuration memory is constructed with a shift register.
Further, the shift register may be commonly constructed by connecting a plurality of D-type flip-flops in series. FIG. 2 shows a schematic diagram of a typical CMOS-D-type flip-flop. In the D-type flip-flop, by connecting an inverter INV and a transmission gate TG in a ring formation, a closed loop is formed. An input signal provided to an input terminal IN is transmitted to an output terminal OUT through a master-slave latch constructed with two closed loops. The D-type flip-flop shown in FIG. 2 has 16 MOS transistors. Therefore, a prior-art shift register constructed with such D-type flip-flops requires a relatively large area on an LSI chip.
Particularly, since the SRAM-program-type FPGA requires hundreds of thousands of stages of shift registers in order to store the configuration data, an extremely large area of the FPGA chip is used for the configuration memory constructed with the shift registers. In general, performance of the FPGA is evaluated by an equivalent gate number per unit area (evaluation index indicating a number of gates corresponding to realizable maximum logic circuits). Therefore, to improve performance of the FPGA, there is a need for miniaturizing a size of the configuration memory constructed with the shift register, and for reducing a ratio of a memory area to an overall chip area.
For miniaturizing the shift register, it is well known that it is advantageous to use a chain-latch-structure shift register. FIG. 3 shows a schematic diagram of a prior-art chain-latch-structure shift register. FIG. 4 shows an illustration for explaining an operation of the prior-art chain-latchstructure shift register shown in FIG. 3.
In FIG. 4, a signal provided to a terminal K, when a switch C is turned on and switches E, F are turned off, passes an inverter D and transmits to an output terminal of the inverter D. After that, when the switch C is turned off and the switches E, F are turned on, a value of the provided signal is held in a closed loop A. After the value in the closed loop A stabilizes and is fixed, the switch C is turned on and the switches E, F are turned off again, and also, switches H and I are turned on. At this time, until an output value of an inverter G changes, it is necessary to operate a switch H and fix an output of an inverter J. If the switch I is turned before the output of the inverter J is fixed, a value to be held in a closed loop B may be lost by a value which has been held in a closed loop A'.
There is the following disadvantage in the above-discussed prior-art chain-latch-structure shift register.
When the above-discussed chain-latch-structure shift register is practically constructed, dispersion in operation performance may occur due to performance of the switches constructing the shift register, wire-load capacitance, timing of a supplied clock, etc. Therefore, it is difficult to obtain a stable operation in that shift register.
Further, in the prior-art programmable logic circuit, there is the following disadvantage.
In general, for methods of constituting the flip-flop using the logic cell in the programmable logic circuit, the following two methods are known:
In both the types, a number of the realizable flip-flops in the programmable logic circuit is determined by a number of the logic cells. Therefore, to increase the number of the realizable flip-flops, it is required to increase the number of the logic cells. However, this requirement causes the chip area of the programmable logic circuit to increase.
In addition, in the prior-art programmable logic circuit and the prior-art programmable-logic-circuit system, before the circuit operation is started, the configuration data is loaded into the configuration memory to determine logic functions of the programmable function unit. After the configuration data is loaded, the programmable logic circuit is operative according to the logic functions determined by the configuration data until all configuration data in the programmable logic circuit is changed.
Namely, the logic functions programmed in the programmable logic circuit are fixed until the operation according to the logic functions is finished. Therefore, to increase the realizable logic functions (or corresponding gate number) in the programmable logic circuit and the programmable-logic-circuit system, it is required to enlarge a size of the logic cell and to increase the number of logic cells. In this case, these requirements also cause the chip area of the programmable logic circuit to increase.